1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which operates in synchronization with a clock.
2. Description of the Related Art
With the progress of semiconductor processes, the operating frequencies of semiconductor integrated circuits have been increasing year by year. The frequencies of clocks to be supplied to the semiconductor integrated circuits have also been increasing accordingly. To miniaturize systems that implement semiconductor integrated circuits, there has also been developed a technology for laminating a plurality of semiconductor integrated circuit chips in a single package to manufacture an SIP (System in Package). In the SIP assembly process, when an SIP is determined to be defective due to mixing of a single failure chip, then the other good chips packaged together must also be rejected. In other words, for the sake of an improved SIP yield and reduced cost, it is important to examine operation margins in detail and reject chips having margin failures through a probe test. Here, the probe test is a test which is conducted with probes put in direct contact with the pads of semiconductor integrated circuits in a wafer state. Incidentally, not only in SIPs but also in ordinary semiconductor integrated circuits, rejecting chips having margin failures through a probe test can improve the manufacturing yield with a reduction in manufacturing cost.
DLL (Delayed Locked Loop) circuits and SMD (Synchronous Mirror Delay) have been proposed for circuitry technologies for achieving the present invention (disclosed in Japanese Unexamined Patent Application Publications Nos. 2000-124796, 2000-122750, and Hei 10-126254).
To evaluate a semiconductor integrated circuit for an operation margin, the frequency of the clock to be used in a probe test must be set at or higher than the maximum operating frequency of the semiconductor integrated circuit. Testing a semiconductor integrated circuit with clocks of higher frequencies, however, requires expensive LSI testers, which can increase the testing cost. On the other hand, the internal clock frequency can be increased, for example, by implementing a PLL circuit inside the semiconductor integrated circuit. Nevertheless, PLL circuits contain analog circuits and thus are large in circuit area. Consequently, the semiconductor integrated circuit may increase in chip area, with an increase in chip cost. Alternatively, for example, it is possible to generate a clock that has pulses in synchronization with the rising edge and falling edge of an external clock which is supplied to the semiconductor integrated circuit from an LSI tester. This technique, however, can only generate a clock having a frequency twice that of the external clock.